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rev. 1.0 12/02 copyright ? 2002 by silicon laboratories SI5020-EVB-10 SI5020-EVB e valuation b oard for si5020 siphy? m ulti -r ate sonet/sdh c lock and d ata r ecovery ic description the si5020 evaluation board provides a platform for testing and characte rizing silicon la boratories? si5020 siphy? multi-rate sonet/sdh clock and data recovery ic. the si5020 cdr supports oc-48/12/3, stm-16/4/1, gigabit ethernet, and 2.7 gbps fec rates. all high-speed i/os are ac coupled to ease interfacing to industry standard test equipment. features ? single 2.5 v power supply ? differential i/os ac coupled ? simple jumper configuration function block diagram refclk + ? z c = 50 ? z c = 50 ? z c = 50 ? z c = 50 ? datain + ? clkout + ? dataout + ? z c = 50 ? z c = 50 ? z c = 50 ? z c = 50 ? pulse generator pattern generator jitter analyzer scope pattern analyzer si5020 lol rext ratesel0 ratesel1 pwrdn/cal 10 k ? jumpers SI5020-EVB rev c test point
SI5020-EVB 2 rev. 1.0 functional description the evaluation board simplifies characterization of the si5020 clock and data recovery (cdr) device by providing access to all of the si5020 i/os. device performance can be evaluated by following the test configuration section below. specific performance metrics include jitter tolerance, jitter generation, and jitter transfer. power supply the evaluation board requires one 2.5 v supply. supply filtering is placed on the bo ard to filter typical system noise components, however, initial performance testing should use a linear supply capable of supplying 2.5 v 5% dc. caution : the evaluation board is designed so that the body of the sma jacks and gnd are shorted. care must be taken when powering the pcb at potentials other than gnd at 0.0 v and vdd at 2.5 v relative to chassis gnd. self-calibration the si5020 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal dspll tm . self-calibration is initiated by a high-to-low transition of the pwrdn/cal signal while a valid reference clock is supplied to the refclk input. on the SI5020-EVB board, a voltage detector ic is utilized to initiate self-ca libration. the voltage detector drives the pwrdn/cal signal low after the supply voltage has reached a specific voltage level. this circuit is described in silicon laboratories application note an42. on the si5 020-evb, the pwrdn/cal signal is also accessible via a jumper located in the lower left- hand corner of the eval uation board. pwrdn/cal is wired to the signal post adjacent to the 2.5 v post. device powerdown the cdr can be powered down via the pwrdn/cal signal. when asserted t he evaluation board will draw minimal current. pwrdn/ca l is controlled via one jumper located in the lowe r left-hand corner of the evaluation board. pwrdn/cal is wired to the signal post adjacent to the 2.5 v post. clkout, dataout, datain these high-speed i/os are wired to the board perimeter on 30 mil (0.030 inch) 50 ? microstrip lines to the end- launch sma jacks as labeled on the pcb. these i/os are ac coupled to simplify di rect connection to a wide array of standard test hard ware. because each of these signals are differential both the positive (+) and negative (?) terminals must be terminated to 50 ? . terminating only one side will adversely degrade the pe rformance of the cdr. the inputs are terminated on the die with 50 ? resistors. to improve the dataout eye-diagram, short 100 ? transmission line segments precede the 50 ? high- speed traces. these segments increase the interface bandwidth from the chip to the 50 ? traces and reduce data inter-symbol-i nterference. please refer to silicon laboratories application note an43 for more details. note: the 50 ? termination is for each terminal/side of a dif- ferential signal, thus the diff erential termination is actu- ally 50 ? +50 ? =100 ? . refclk refclk is used to center the frequency of the dspll? so that the device can lock to the data. ideally the refclk frequency should be 1/128th, 1/32nd, or 1/16th the vco frequency and must have a frequency accuracy of 100 ppm. internally, the cdr automatically recognizes the refclk frequency within one of these three frequency ranges. typical refclk frequencies are given in table 1. refclk is ac coupled to the sma jacks located on the top side of the evaluation board. ratesel ratesel is used to configur e the cdr to recover clock and data at different data rates. ratesel is a two bit binary input that is controlled via two jumpers located in the lower left-hand corner of the evaluation board. ratesel0/1 are wired to the ce nter posts (signal post) between 2.5 v and gnd. fo r example, the oc-48 data rate is selected by jumping ratesel0 to 0.0 v and ratesel1 to 0.0 v. the table given on the evaluation board lists approximate data rates for the jumper configurations shown in figure 1. applicat ions with data rates within 7% of the given data rate are also accommodated. table 1. typical refclk frequencies sonet/sdh gigabit ethernet sonet/ sdh with 15/14 fec ratio of vco to refclk 19.44 mhz 19.53 mhz 20.83 mhz 128 77.76 mhz 78.125 mhz 83.31 mhz 32 155.52 mhz 156.25 mhz 166.63 mhz 16
SI5020-EVB rev. 1.0 3 figure 1. ratesel jumper configurations loss-of-lock (lol) lol is an indicator of the relative frequency between the data and the refclk. lol will assert when the frequency difference is greater than 600 ppm. in order to prevent lol from de-asserting prematurely, there is hysterisis in returning from the out-of-lock condition. lol will be de-asser ted when the frequency difference is less than 300 ppm. lol is wired to a test poin t which is located on the upper right-hand side of the evaluation board. test configuration the three critical tests that are typically performed on a cdr device are jitter transfer, jitter tolerance, and jitter generation. by connecting th e si5020 evaluation board as shown in figure 2, all three measurements can be easily made. refclk should be within 100 ppm of the frequency selected from table 1. ratesel must be configured to match the desired data ra te, and pwrdn/cal must be unjumpered. jitter tolerance : referring to fi gure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ? ). during this test the jitter analyzer causes a modulation on the data patt ern which drives the datain ports of the cdr. the bit-error-rate (ber) is monitored on the pattern analyzer. the modulation (jitter) frequency and amplitude is recorded when the ber approaches a specified threshold. jitter generation : referring to figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ? ). during this test, there is no modulation of the data clock, so the data that is sent to the cdr is jitter free. the jitter analyzer measures the rms and peak-to-peak ji tter on the cdr clkout. thus, any jitter measured is jitter generated by the cdr. jitter transfer : referring to figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ? ). during this test the jitter analyzer modulates the data pattern and data clock reference. the modulated data clock reference is compared with the clkout of the cdr. jitter on clkout relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. gnd 2.5 v 2488 mbps gnd 2.5 v 1244 mbps gnd 2.5 v 155 mbps gnd 2.5 v 622 mbps ratesel1 ratesel0 pwrdn/ cal ratesel1 ratesel0 ratesel1 ratesel0 ratesel1 ratesel0 pwrdn/ cal pwrdn/ cal pwrdn/ cal
SI5020-EVB 4 rev. 1.0 figure 2. test configuration for jitter tolerance, transfer, and generation jitter analyzer pattern analyzer pulse generator pattern generator modulation source synthesizer signal source 2.5 v refclk datain clkout dataout scope SI5020-EVB refclk+ datain+ dataout+ clkout+ gpib dataout? clock data clock+ fm gpib gpib clkout? refclk? datain? gpib ? + + ? + ? + ? + ?
SI5020-EVB rev. 1.0 5 jp4 c6 0603 0.1uf c16 0603 100pf jp2 vdd vdd j1 jc 142-0701-801 1 2 sig body vdd c1 0603 0.1uf r2 0603 2.5k c7 0603 0.1uf c13 0603 100pf jp3 v? u4 max6376xr23-t 3 1 2 vcc gnd out l1 1206 blm31a601s vdd j4 jc 142-0701-801 1 2 sig body c8 0603 0.1uf j3 jc 142-0701-801 1 2 sig body c5 0603 0.1uf c15 0603 100pf c3 0603 0.1uf r1 0603 10k u5 si5020 6 12 13 16 17 20 19 15 9 10 4 5 1 2 7 11 3 8 18 14 lol dout- dout+ clkout- clkout+ ratesel1 ratesel0 pwrdn/cal din+ din- refclk+ refclk- rext vdda vddb vddc gnda gndb gndc vddd j5 jc 142-0701-801 1 2 sig body c4 0603 0.1uf c9 0805 do not install j6 jc 142-0701-801 1 2 sig body j8 jc 142-0701-801 1 2 sig body j2 jc 142-0701-801 1 2 sig body c2 0603 0.1uf 2.5v j9 mkdsn 2,5/3-5,08 1 2 pos1 pos2 j7 jc 142-0701-801 1 2 sig body jp1 vdd c12 tantalum 10uf vdd figure 3. si5020 schematic
SI5020-EVB 6 rev. 1.0 bill of materials si5020evb assy rev b-02 bom reference part desc part number manufacturer c1,c2,c3,c4,c5, c6,c7,c8 cap, sm, 0.1uf, 0603 c0603x7r160-104kne venkel c12 cap, sm, 10 uf, tantalum, 3216 ta010tcm106kar venkel c13,c15,c16 cap, sm, 100 pf, 16v, 0603 c0603c0g500101kne venkel jp1,jp4 connector, header, 2x1 2340-6111tn or 2380-6121tn 3m jp2,jp3 connector, header, 3x1 2340-6111tn or 2380-6121tn 3m j1,j2,j3,j4,j5,j6, j7,j8 connector, sma, side mount 901-10003 amphenol j9 connector, power, 2 pos 1729018 phoenix contact l1 resistor, sm, 0 ohm, 1206 cr1206-8w-000t venkel r1 resistor, sm, 10k, 1%, 0603 cr0603-16w-1002ft venkel r2 resistor, sm, 2.55k, 1%, 0603 cr0603-16w-2551ft venkel u4 max6376xr23-t max6376xr23-t maxim u5 si5020 si5020-bm silicon laboratories pcb printed circuit board SI5020-EVB pcb rev c silicon laboratories no load c9 spare,0805
SI5020-EVB rev. 1.0 7 figure 4. si5020 silkscreen
SI5020-EVB 8 rev. 1.0 figure 5. si5020 component side
SI5020-EVB rev. 1.0 9 figure 6. si5020 solder side
SI5020-EVB 10 rev. 1.0 document change list revision 0.41 to revision 1.0 ? ?preliminary? language removed. evaluation board assembly revision history assembly level pcb si5020 device assembly notes a-01 a a assemble pe r bom rev a-01. b-01 b b assemble pe r bom rev b-01. b-02 c b assemble pe r bom rev b-02.
SI5020-EVB rev. 1.0 11 notes:
SI5020-EVB 12 rev. 1.0 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and siphy are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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